Monday, August 29, 2005


I haven't blogged anything for days (weeks?). I am very busy nowadays with the usual acad work load. It's a good thing my nose is not yet clogged that I could still breathe in some air.

This semester, I may say, is by far the most challenging one. Actually, the EEE majors I am taking are meant to be the last before I get to think for our thesis project. Ideally speaking, if I pass all my units this sem, I would only have to take 13 units all in all next semester! Aside from that, not all of it are EEE subjects anymore! Wouldn't it be fun?!

The problem is the current sem. CoE 115[Microprocessor Design] takes a lot of time. Plus the exams are hell! Most dreaded subject in EEE (aside from 198 which should be a given). CoE 141 [Digital IC Design] wants all the attention done on the lab work. Too much exposure on Cadence... whew! Oh, its hard to balance these subjects as it is accompanined by the theoreticals like EEE 107 [Communication Systems] and EEE 53 [Electronic Circuits 2].

Problems, problems. No wonder why my hair turns grey easily. I always think of the problem. Better think of the solutions too, a#sh+le!


posted by ScIoN 2:09 AM |

Thursday, August 18, 2005

Beta Blogging [This site still under construction]

This site is still under construction. I am still currently using friendster blogs; thus, most of my posts here are just copy-pasted from that site. Yehey! For now, I already have a site meter.. hehehe. Somebody teach me something! hahaha!


posted by ScIoN 10:03 PM |

Monday, August 08, 2005

Fuse Failed...Not!

Warning: Do you really want to read this rant of mine?

I should had posted this last week, but due to the sad demise of Roco, I could just not share my rant at that time. Last thursday was our due date for our MP in CoE111 (Advanced Digital Design). We are to program a switched Arithmetic Logic Unit using VHDL (Very high speed integrated circuit Hardware Description Language). I did some late night-early morning programming as I was just able to sneak in a 1 hour nap for the whole session. You may blame me for cramming the night out but actually there were things that just wasted my time during the whole process.

I was able to download Aldec's (name of company) VHDL compiler; but then I could not figure out how to work out with its simulator. I was expecting some waveform testbenches but it came out differently. Consequently, I spent some time asking through ym; still, couldn't figure it out. Good thing I had this copy of Xilinx, which was the actual software used in our lab class. Problem is, I could not make the ISE simulator work. Even though I got to have some student's license from the net, the integrated version just won't work. The only thing I had done the whole night was to code and check the syntax. No testbench done.

I believe I had wasted much more time in figuring out things rather than coding itself. I call it a waste because nothing productive came out of it. I was not able to use ALDEC, and I was not able to testbench through XILINX. Due date is near and still I don't have some documentation at hand. I planned to finish everything that day anyway.

I did everything I can. I maximized my time, planned to cut-class in EEE107 (good thing there really was no class) and had to sit-in in a part of the lab class (my turn should still be at 4pm, good thing there was still a vacant PC). I became pretty confident that my code would work since the syntax was correct. Thus, I started my documentation in class. I figured out that it was the important thing to be done first because it is the very physical evidence that I had done the Machine Program.

Later on, Teejay (the SA) started checking out on our work. He checked through the testbenches of our functions. As I started to try and testbench mine, an error message appeared, indicating a "fuse failed, must recompile...blah blah". The 2 SAs ("kuya" Teejay and Ige) were present, and both of them don't know what the error message meant. It was weird that I had a correct program syntax, was able to produce an RTL schematic, but was not able to testbench. Is it me, my program or the darn thing I'm using?

Frustation. That's the word. After a sleepless night of coding, nothing seemed to happen. It was only the add function that worked and that I was able to show. Weird. Only one function out of many, and that one function was really just a give away. Though only PI had a full working program, at least the others were able to show a majority of working functions. What would my MP grade be then? I don't even have a hard copy of my docu!

Fuse Failed. What an error message. The phrase haunts me. It is even used against me (by Elma!!). I had been thinking about it the whole weekend. Planned to work during the UPCAT days, but nothing happened. I guess I had to unwind a bit and pull out the stress.

I had done nothing about it during the weekend... until this 1130pm, Sunday. I tried to work my Xilinx again. Walla! The Modelsim integrated with my Xilinx worked! Weird. Why did it not work before?!! Tried to make some testbenches... compiled... put inputs... simulate... and it worked. IT WORKED.

What happened back then?!! In the corporate world, I could have sued everyone for giving me a hard time. Still, thank God!

**Note: I really had not checked its full functionality yet, but I'm just as happy that the "fuse did not really fail"... or whatever it meant. It was the darn thing. Yeah, it was...


posted by ScIoN 1:01 AM |

Saturday, August 06, 2005

Death of a Statesman

Thanks for the weekend, I had the luxury to check the net again after a long and still unfinished business with VHDL programming. In as much as I would like to blog about gEEEky stuffs, I can't help but to give some space for my favorite politician.

Former Senator Raul Roco recently passed away 9:16am, yesterday. Sad but true. I first saw this in one of Rechie's friendster bulletin posts and had verified it through inq7.

Roco always stand and speak with dignity. He is the most respectable politician I could think of. As of this moment, I could not think of any one else who could be "next" as my new favorite. The politicians we see today all seem to be tainted. I remember the time when Gloria was well-loved that she topped the senatorial elections. Now, look at her scrambling at the tip of her reign.

Roco should have been the next president. In the first months of candidacy filing, he was a prominent figure as his opponents are yet undecided to run. The blueprints of his reforms had been set. He was very much ready to serve.

A characteristic of the opposition was that they rely too much on popularity in order to win. FPJ did not want to be President, yet he got flattered by his fans' clamor for him to run. Gloria promised not to run, but she wanted to make her father proud by being president-elect. Eventually, the votes against the popular was divided. Gloria gained Roco's votes as some doubted on his winnability against an actor. Gloria being the lesser evil. Another batch of votes wasted for such lame reasoning.

Now, there seems to be a trend about Gloria's presidential opponents. After FPJ, next was Roco. Go figure. Is this God's way of saying Gloria deserved the position? Or does it just mean that Ping Lacson is next to lay down in a funeral bed?

Anyway, to Mr. Raul Roco, may you rest in peace. In Japanese culture, one can say that "he died a good death". The Philippines need people like him. Badly.


posted by ScIoN 10:49 AM |

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Location: Quezon City, Metro Manila, Philippines

ScIoN is a former Systems Engineer in Japan who specialized in industrial imaging and digital hardware design. He is now back in the Philippines pursuing graduate studies in Finance at the University of the Philippines - Diliman.



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